The present invention relates to transfer function generation in electronic systems and, more particularly, to novel apparatus for facilitating implementation of any desired single-valued input/output, transfer and the like functions in an electronic system.
Many electronic systems require implementation of a specific transfer function which maps a present input signal into a corresponding output signal. As an example, and without limitation, consider an ultrasonic imaging system of the phased-array, sector-scanning (PASS) type; a plurality of transducers are arrayed to transmit and receive vibratory energy, with the output of each transducer being processed in a separate channel of electronic circuitry. All channels are identical, at least at the block level and typically contain at least one analog-to-digital converter (ADC), which is utilized for converting the analog RF signal from each channel transducer, at any instant, into a digital data word for processing. The ADC(s) in each channel carry out conversions at a sample frequency of at least two times, and usually four times, the maximum operating imager frequency. In an ultrasonic medical imager utilizing signals of up to 10 MHz, each of the N channels (where N is presently on the order of 64) requires the use of at least one ADC of 7 or 8 bit output resolution, and operating at a 20 or 40 MHz sampling rate; those skilled in the art will immediately realize that seven or eight bit ADC resolution is insufficient to provide the at least 70 dB of instantaneous dynamic range required in each channel of the imaging system. In order to use a linear ADC of lesser resolution to realize a large imaging system dynamic range, the method (described and claimed in co-pending application Ser. No. 207,532, filed June 16, 1988, now U.S. Pat. No. 5,005,419 assigned to the assignee of the present invention and also incorporated here in its entirety by reference) used provides predetermined nonlinearity in front of the linear ADC, to compress the analog signal prior to conversion to a digital data word; the digital data word is then further processed in accordance with another non-linear mathematical function which is selected to be the inverse (expansion) of the previously-employed mathematical (compressive) function, so that the value of the expanded digital data words are again linearly related to the value of the input analog RF (echo) signal voltages provided to the input of the compressive amplifier. The inverse (expansion) non-linear relationship may be provided in the ADC itself, or may be provided in a subsequent stage, which may utilize a look-up table approach. The latter approach is particularly desirable if a compression amplifier approximates a power law function and a static-random-access-memory (SRAM) circuit provides an output signal which preserves both the input sign and the inverse power law exponent. For example, utilizing an ADC with a 7-bit-wide output data word, in a system requiring an 11-bit-wide data word for realization of the required instantaneous dynamic range, the power law (i.e. log(V.sub.out)=k log (V.sub.in)) results in k=0.6 for the compressive stage, and an expansion stage constant k'=1/k=5/3.
While the above-described subsystem (i.e. compression analog amplifier, ADC and expansion digital RAM look-up remap stage) allows the instantaneous system dynamic range to be increased to the desired level, utilizing the preselected nonlinear compressive/expansive complementary functions, we have found that any desired single-valued function can be provided simultaneous with the ability to remove many other system nonlinearities, and also to remove certain classes of nonlinearities generated by imperfections in the channel apparatus. It is highly desirable to provide a subassembly which allows any desired single-valued function to be implemented and to provide for simultaneous multiple functions, such as inverse dynamic range decompression, correction of ADC and other component nonlinearities, correction of subassembly gain differences and the like.